Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge which represents information to be stored, and an access transistor which is connected with the storage capacitor. The access transistor comprises a first and a second source/drain regions, a channel connecting the first and the second source/drain regions as well as a gate electrode controlling an electrical current flow between the first and second source/drain regions. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of a word line and is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out. In addition, by addressing the access transistor and transmitting an information signal via a bit line, an information is stored in the corresponding memory cell, which is assigned to the specific word line and bit line.
In the currently used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor. In a trench capacitor, for example, the storage electrode can be disposed in a trench which extends in the substrate in a direction perpendicular to the substrate surface. The storage electrode is isolated from the sidewalls of the trench by a dielectric layer acting as the capacitor dielectric, the sidewalls of the trench forming a counter electrode.
According to another implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
FIG. 10 illustrates a cross-sectional view of an exemplary DRAM memory cell comprising a stacked capacitor. In FIG. 10, an access transistor comprising a first source/drain region 51 and a second source/drain region 52 is formed in a substrate 1. A gate electrode 53 is provided so as to control an electrical current flow between the first and the second source/drain regions 51, 52 respectively. The gate electrode 53 forms part of a word line 7. A bit line 8 is connected via a bit line contact 81 with the second source/drain region 52. As is illustrated in FIG. 10, the storage capacitor 2 is disposed above the semiconductor substrate surface 10. In particular, the storage capacitor 2 comprises a storage electrode 20 as well as a counter electrode 210. Both capacitor electrodes are formed of n+-doped polysilicon. A dielectrical layer 211 is disposed between the storage electrode and the counter electrode. A capacitor contact 24 electrically connects the first source/drain region 51 with the storage electrode 20. A BPSG (boron phosphorous silicate glass) layer 54 is disposed above the substrate surface 10 and electrically isolates the capacitor components from the substrate surface.
For future DRAM technologies, an increased cell capacitance for high performance and low power applications is required. In the structure of FIG. 10, the cell capacitance can be increased by increasing the height of the stacked capacitor. In particular, by increasing the height of the capacitor with respect to the width of the capacitor, or, differently stated, by increasing the aspect ratio of the storage capacitor, the cell capacitance can be increased while reducing the size of the memory cell. At present, typical aspect ratios amount to 20 to 30. Nevertheless, with current technologies, it appears to be difficult to further increase the aspect ratio of the storage capacitor. In addition, with higher aspect ratios, the mechanical stability of a storage capacitor which is implemented as a cylinder becomes a serious problem. At present, the height of the cylinders amounts to approximately 1.5 to 2 μm. As can for example be gathered from FIG. 10, at higher aspect ratios, the cylinders become more fragile and, additionally, a problem of sticking cylinders is likely to occur.
The article “Robust Memory Cell Capacitor using Multi-Stack Storage Node for High Performance in 90 nm Technology and Beyond”, by Lee et. al, 2003 Symposium on VLSI Technologies, proposes a storage node structure comprising a cylinder shaped capacitor which is stacked on a box-shaped capacitor. For obtaining such a storage node, the electrode and the interelectrode dielectricum have to be deposited with a high aspect ratio.
In view of the above, there is a need to provide a storage capacitor having a high aspect ratio as well as a relatively simple geometry, so that it can be manufactured with a low degree of complexity.